A conventional data source circuit serially transmits multi-bit words, periodically presented in parallel to the conventional data source circuit input, by sequentially toggling a flip-flop output when a bit to be transmitted differs from an immediately previous transmitted bit. As is discussed below, the conventional data source circuit fails to perform as desired at high data transmission rates.
Referring now to FIG. 1, there is shown an example of a conventional data source circuit 10. Specifically, the conventional data source circuit of FIG. 1 serially transmits individual bits of 7-bit words; the 7-bit words are periodically and continuously presented in parallel to a data input 20. Since 7-bit words are presented to the data input 20 periodically and continuously, the individual bits of each 7-bit word presented must be transmitted at a rate such that data does not "back up". Such a "back up" condition is known in the art as data overwrite.
If, for example, the 7-bit words are presented to input 20 at a rate of 5 MHz, the individual bits must be transmitted along data transmission line 22 at a 35 MHz rate. The conventional data source circuit 10 accomplishes this 35 MHz data transmission scheme as explained below.
Referring still to FIG. 1, separate data bits D.sub.a -D.sub.g of a 7-bit word to be transmitted are presented to separate ones of a series of bit-change detectors 21a-21g, respectively. The bit-change detectors are a series of 2-input XOR devices. XOR device 21b, for example, has presented to its inputs bits D.sub.b and D.sub.a. Likewise, XOR device 21c has presented to its inputs bits D.sub.c and D.sub.b, and so on up to XOR device 21g, which has as its inputs bits D.sub.g and D.sub.e.
Finally, XOR device 21a has as its inputs bits D.sub.a and D.sub.g. More precisely, the bit D.sub.g input to XOR device 21a is always D.sub.g of the 7-bit word previously presented to data input 20. But D.sub.g of the previously presented 7-bit word must thus be buffered so that it is not overwritten by bit D.sub.g of a currently-presented 7-bit word. The bit D.sub.g buffering mechanism is not shown in FIG. 1.
The result of daisy-chaining the 2-input XOR devices 21a-21g is that a particular XOR device asserts at its output a "bit-change" signal only when a to-be transmitted bit differs from the immediately previous transmitted bit. For example, the output of XOR device 21c is asserted only if bit D.sub.c differs from bit D.sub.b ; and the output of XOR device 21a is asserted only if bit D.sub.a differs from bit D.sub.g of the previously presented word.
The outputs of the XOR devices 21a-21g (i.e. the results of the "bit change" comparisons) are presented to second inputs 25a-25g, respectively, of 3-input AND devices 24a-24g, respectively.
Meanwhile, a 5 MHz periodic source clock signal, CLK.sub.0, is presented to clock input 29. A new 7-bit data word is available at data input 20 coincident with each rising edge of clock signal CLK.sub.0. From clock input 29, CLK.sub.0 is passed through seven successive delay elements 31a-31g, respectively, to produce delayed clock signals CLK.sub.a -CLK.sub.g, respectively. CLK.sub.a -CLK.sub.g are of the same period and frequency as CLK.sub.0. The importance of which will be seen below, each delay element 31a-31g must be chosen to delay a signal presented to it by approximately the time needed to transmit a data input bit. That is, for a 35 MHz transmission rate of individual bits, each delay element 31a-31g must delay the delayed clock signal presented to by approximately 28 nsecs. The timing diagram of FIG. 2 shows the relative timing of CLK.sub.0 and the delayed clock signals CLK.sub.a -CLK.sub.g.
Delayed clock signals CLK.sub.a -CLK.sub.g, respectively, are presented to first inputs of 3-input AND devices 23a-23g, respectively.
Delayed clock signals CLK.sub.a -CLK.sub.g, respectively, are also presented to pulse-width control inverters 33a-33g, respectively. Pulse-width control inverters 33a-33g then output periodic pulse width control signals PWC.sub.a -PWC.sub.g, respectively. As shown in the timing diagram of FIG. 2, PWCa-PWCg, respectively, are signals inverted and delayed relative to CLK.sub.a -CLK.sub.g, respectively.
The importance of which will also be discussed in more detail below, each of the pulse-width control inverters 33a-33g must be chosen so that a signal presented to it is delayed by approximately half the time needed to transmit a data input bit. That is, for a 35 MHz transmission rate of individual bits, the pulse-width control inverters must delay the delayed clock signal presented to it by approximately 14 nsecs.
PWC.sub.a -PWC.sub.g, respectively, are presented to third inputs 27a-27g, respectively, of 3-input AND devices 24a-24g.
Only when the delayed clock signal and pulse width control signal associated with a particular bit-change signal (i.e. the ones presented to the same 3-input AND device as the particular bit change signal) are both high can the bit-change signal be transmitted to the output of the 3-input AND device. Because of the chosen delay times of delay elements 31a-31g and pulse width controllers 33a-33g, at any one time there is only one delayed clock signal and associated pulse-width control signal combination where both the delayed clock signal and the pulse-width control signal are high together. As a result, bit-change signals present at the XOR devices 21a-21 g are transmitted one at a time.
It is important that these bit-change signals are transmitted one at a time because the transmitted bit-change signals are presented to inputs of a 7-input OR device 39, and an output of the 7-input OR device 39 is connected to a clock input 36 of a toggle flip-flop 34. Because the toggle flip-flop 34 has its inverted data output tied to its data input, each time the output of the 7-input OR device pulses (i.e. a bit-change signal has been transmitted), to signal a bit-change in the input data, the output of the toggle flip-flop clocks to its opposite state. That is, when the bit-change signals are transmitted by the 3-input AND devices 24a-24g one at a time, the output of the 7-input OR device represents the one-at-a-time transmitted bit-change signals. In this case, then, the output 22 of the toggle flip-flop 34 represents the serial transmission of the data bits D.sub.a -D.sub.g of the 7-bit data words periodically and continuously presented to data input 20.
The conventional data source circuit 10 of FIG. 1 works well when the data to be transmitted is presented to its input 20 at a relatively low rate. However, there is an ever-increasing need for higher data-rate transmission systems. For example, with the advent of multimedia (i.e. integrated video, audio, and data), and its heavy data and throughput demands, there is a growing need for higher-rate data transmission links between internal cards of personal computers. Furthermore, there is a need for large amounts of data to be transmitted quickly among distributed computer resources.
Conventional data source circuits such as the conventional data source circuit 10 of FIG. 1 fail to perform as desired at today's required higher data transmission rates. The problem is that, in a worst-case condition of each transmitted bit being different from an immediately previous transmitted bit, a stable periodic signal must be generated at the CLK node of toggle flip-flop 34 at a frequency equal to the desired data transmission rate.
Because of inherent process limitations, even with late generation high-speed logic fabrication technology such as 1 .mu.m CMOS, it is presently impossible to generate such a periodic signal at frequencies equal to high desired data transmission rates.
For example, to transmit 7-bit words which all strictly contain alternating "1"'s and "0"'s, at a rate of 350 MHz, with the conventional data source circuit 10 of FIG. 1 requires the generation of a 350 MHz stable clock (that is, a clock which transitions 700.times.10.sup.6 times per second, or 1 transition per approximately 1.4 nsec) at the CK node of the toggle flip-flop 34. Given a basic element delay of 1 nsec for the pulse width controller inverters 33a-33g, it is presently impossible to implement such a clock in a 1 .mu.m CMOS fabrication technology.
Furthermore, even if it were possible to implement such a 350 MHz clock in a 1 .mu.m CMOS fabrication technology, the sequential element (i.e. the toggle flip-flop 34) of the conventional system would not be fast enough to be able to respond correctly to a 350 MHz clock signal.
Also, with each increase in speed that comes with advances in fabrication technology, there will be a concomitant requirement for transmission rates beyond the capability of the conventional data source circuit which uses even the most advanced fabrication technology. Furthermore, if a suitable solution is available using more primitive fabrication technology, this solution may be less expensive than a solution which requires the most advanced technology.